Rethinking AI power delivery

Hans Hasselby-Andersen, CEO of Lotus Microsystems, explains why legacy power architectures can no longer meet the demands of modern AI accelerators. The company’s vStrata platform combines electrical, thermal and mechanical optimisation into a single low-profile design, delivering power beneath the processor while managing heat at the source.

The explosive growth of artificial intelligence has forced every layer of computing infrastructure to evolve at an unprecedented pace. Processor performance continues to advance, memory bandwidth is increasing, and cooling technologies have become increasingly sophisticated. Yet one of the most fundamental challenges facing AI infrastructure lies in a less visible part of the system: power delivery.

As AI accelerators move into the kiloampere current regime, conventional board-level power architectures are approaching their physical limits. Longer electrical paths, increasing resistive losses, rising thermal densities and shrinking board space are combining to create bottlenecks that can no longer be solved simply by incremental improvements.

According to Lotus Microsystems, the industry has reached a point where traditional approaches to power distribution are fundamentally mismatched to modern AI hardware. Its recently announced vStrata platform proposes a complete architectural rethink, replacing conventional horizontal power delivery with a vertically integrated approach that positions power conversion directly beneath the processor.

Rather than presenting another incremental voltage regulator improvement, the company argues that the future of AI infrastructure depends on treating electrical delivery, transient response and thermal management as a single engineering problem.

When legacy architecture meets modern AI
For decades, horizontal power delivery has served computing systems well. Voltage regulation has traditionally been positioned away from the processor, with power distributed across multilayer printed circuit boards before reaching the point of load. That model worked because processor current requirements remained within practical limits. Today’s AI accelerators represent an entirely different class of device.

Modern XPUs routinely require thousands of amps during peak workloads, creating enormous demands on every stage of the power delivery network. Transporting these currents across conventional PCB traces inevitably introduces resistance, energy loss and heat generation before power even reaches the processor itself.

From Lotus Microsystems’ perspective, this represents an architectural rather than a component-level problem.

Instead of attempting to optimise increasingly inefficient horizontal current paths, vStrata effectively removes them. By placing the power delivery module directly beneath the AI processor, electrical path lengths are reduced to almost zero, eliminating much of the resistive loss associated with conventional board-level routing.

The concept appears deceptively straightforward, yet its implications extend well beyond improving converter efficiency. It fundamentally changes how power is distributed throughout the system.

Breaking down the power-thermal divide
Perhaps the most significant aspect of the vStrata philosophy is that it rejects the traditional separation between power engineering and thermal engineering.

Historically, these disciplines have been treated independently. Power delivery engineers optimise conversion efficiency and electrical performance, while thermal specialists address the resulting heat through heatsinks, airflow or liquid cooling. Integration often occurs relatively late in the design cycle.

That separation becomes increasingly problematic as power densities continue to climb.

At hyperscale AI power levels, electrical and thermal performance are no longer independent variables. Every watt lost during conversion immediately becomes heat that must be removed. Every increase in operating temperature influences efficiency, reliability and long-term system performance.

Rather than viewing thermal management as a downstream problem, vStrata integrates both functions within the same physical structure.

Central to this approach is Lotus Microsystems’ silicon power interposer technology. Electrically, it provides the high-performance interconnect required for vertical power delivery. Thermally, silicon’s excellent conductivity creates a direct pathway for removing heat from the source before hotspots can develop.

For system designers, this represents a shift from balancing competing electrical and thermal compromises toward working with a single co-engineered platform in which both characteristics are optimised simultaneously.

Beyond converter efficiency
One of the headline claims surrounding the vStrata platform is a reported 50% reduction in power conversion losses.

While such improvements naturally attract attention, Lotus Microsystems attributes the gain to a combination of architectural decisions rather than a single technological breakthrough.

The first contribution comes directly from the vertical topology itself.

Reducing electrical path lengths dramatically decreases resistive losses that traditionally accumulate between the voltage regulator and processor. Less resistance translates directly into higher overall efficiency.

The second contribution comes from redesigning the converter architecture itself.

According to the company, conventional integrated voltage regulators encounter an efficiency ceiling as current levels increase. Rather than refining existing architectures, vStrata employs a fundamentally different converter topology intended to bypass those inherent limitations.

Interestingly, the silicon interposer itself is not presented as the primary source of efficiency improvement. Instead, its role is enabling sustained operation at these efficiency levels by managing the remaining thermal load.

Even if conversion losses are reduced by half, systems delivering kiloampere-class currents still generate significant heat. Efficient thermal extraction therefore remains essential for maintaining stable operating conditions and preventing localised thermal hotspots.

The result is an architecture in which electrical efficiency and thermal transport reinforce one another rather than acting as competing constraints.

Meeting the transient challenge
Steady-state efficiency represents only one aspect of AI power delivery.

Modern AI processors routinely transition between workloads that demand enormous current changes within nanoseconds. Any delay in supplying that current risks voltage droop, performance throttling or, in extreme cases, processor instability.

Traditional designs address this challenge by surrounding processors with large banks of external capacitors that act as temporary energy reservoirs during rapid load transitions.

While effective, these capacitor arrays consume valuable board space while introducing additional electrical distance between stored energy and the processor itself.

Lotus Microsystems has taken a different approach
Rather than relying on external capacitance distributed around the processor package, vStrata integrates the required energy reservoir directly within the power delivery module.

Positioning this energy storage immediately beneath the processor significantly reduces response latency while simplifying board layout.

The company reports transient response capability exceeding 10 A/ns, allowing the integrated power system to respond rapidly enough to satisfy the sudden current demands characteristic of large AI accelerators. Beyond the electrical performance benefits, eliminating extensive capacitor banks also releases valuable PCB real estate—an increasingly important consideration as servers continue to integrate more compute resources into fixed rack dimensions.

Preventing heat rather than fighting It
Thermal management has become one of the defining challenges of hyperscale AI deployment.

Liquid cooling, advanced cold plates and increasingly sophisticated airflow strategies have all emerged to manage escalating processor power levels. Yet these approaches largely share the same philosophy: remove heat after it has already been generated. Lotus Microsystems advocates a different perspective.

Rather than focusing exclusively on cooling technology, the company argues that the greatest opportunity lies in preventing unnecessary heat generation in the first place.

Lower conversion losses naturally produce less waste heat
The remaining thermal energy is then transported away through the silicon power interposer, which functions as a highly conductive thermal pathway immediately beneath the processor. Instead of allowing hotspots to form before dissipating them through external cooling systems, heat begins moving away from its source almost immediately after it is generated. The company reports point-of-load temperature reductions of up to 25°C. Such improvements extend beyond simply lowering processor temperatures.

Reduced operating temperatures typically improve long-term component reliability, increase expected lifetime and provide greater thermal headroom for future processor generations. Lower baseline temperatures may also enable greater compute density within existing rack envelopes by reducing cooling constraints.

Viewed from a system perspective, the strategy effectively combines two complementary mechanisms: generating less heat during power conversion while simultaneously improving the efficiency with which the remaining heat is removed.

Integration without disruption
Technical superiority alone rarely guarantees adoption within the semiconductor industry.

Infrastructure vendors have invested heavily in existing reference designs, controller ecosystems and development workflows. Any new architecture requiring wholesale redesign presents a significant barrier to deployment.

Lotus Microsystems appears to have recognised this challenge from the outset.

Although vStrata introduces a fundamentally different physical power architecture, the platform has been designed to remain compatible with existing Tier 1 reference designs and commercially available power management controllers.

Rather than asking processor vendors and system integrators to rebuild their entire design ecosystem, the objective is to integrate within existing development environments.

This compatibility strategy could prove particularly important during early adoption. Silicon vendors can continue using familiar controllers, established design methodologies and proven software infrastructure while evaluating the performance advantages offered by vertical power delivery.

Reducing engineering friction may ultimately prove as important as improving efficiency.

Collaboration before tape-out
Another notable aspect of the programme has been the level of collaboration preceding silicon tape-out.

Rather than developing the architecture independently before approaching customers, Lotus Microsystems reports extensive engagement with leading XPU and AI infrastructure partners throughout the design process.

This collaborative approach appears to have shaped the platform’s development around practical deployment challenges rather than theoretical optimisation.

According to the company, early feedback following tape-out has reinforced confidence that the platform addresses genuine bottlenecks facing hyperscale AI designers.

Among the most frequently cited advantages has been improved compute density.

Rack space remains one of the most valuable resources within hyperscale data centres. Any technology capable of reducing the physical footprint of power delivery while simultaneously lowering thermal constraints creates opportunities to deploy additional compute resources within existing infrastructure.

This directly influences total cost of ownership.

Higher compute density improves utilisation of expensive facilities, networking infrastructure and cooling systems while potentially reducing overall capital expenditure for equivalent AI capability.

For hyperscale operators deploying tens of thousands of accelerators, even modest gains at the server level can translate into substantial operational savings.

The road to deployment
Although vStrata represents an ambitious architectural shift, commercial deployment will necessarily proceed in stages.

Engineering samples are scheduled to enter an early access programme during the third quarter of 2026, allowing selected partners to transition from theoretical evaluation toward practical system integration. This phase will provide the first opportunity to validate laboratory performance under real-world AI workloads and hyperscale operating conditions.

Following engineering sampling, the focus shifts toward collecting operational data from pilot deployments before progressing through qualification and eventually entering volume production.

These milestones will determine whether the architecture delivers its promised benefits outside controlled demonstration environments. For the broader industry, the coming year may prove particularly significant. If vertical power delivery demonstrates measurable improvements in efficiency, thermal performance and compute density within production-scale AI systems, it could influence how future accelerators are architected from the outset.

A new direction for AI power electronics
The demands of AI have repeatedly forced engineers to reconsider long-established assumptions about computing architecture.

Memory hierarchies have evolved, cooling technologies have transformed and interconnect bandwidth continues to increase. Power delivery may now be approaching a similar inflection point. The challenges facing modern AI infrastructure are increasingly driven by physics rather than incremental optimisation. Transporting kiloampere currents across conventional PCB layouts while maintaining efficiency, thermal stability and transient performance becomes progressively more difficult as processor power continues to rise.

vStrata represents one possible answer to that challenge—not through incremental refinement, but through architectural reorganisation. Its central proposition is that electrical delivery and thermal management can no longer be treated as independent disciplines. Instead, they must become a unified design problem in which converter topology, energy storage, interconnection and heat removal are engineered as a single integrated system.

Whether vertical power delivery ultimately becomes an industry standard remains to be seen. However, as AI infrastructure continues its relentless scaling trajectory, the underlying argument appears increasingly compelling. Future advances in processor performance may depend not only on faster silicon, but on fundamentally rethinking how electrical energy reaches it in the first place.