Saras targets the AI power-delivery challenge
As AI and HPC push power densities ever-higher, Shaun Bowers of Saras Micro Devices explains how embedded passives, advanced packaging and vertical power delivery will help.
By Rebecca Pool, Technology Editor
Earlier this year, former Amkor executive, Shaun Bowers, joined US-based Saras Micro Devices as senior vice president of product management – just as the firm scales manufacturing of its PCB-embedded passive modules for integrated power delivery. Power Electronics caught up with Bowers to discuss the growing power-delivery challenges facing AI and high-performance computing, the role of embedded passives and advanced packaging, and Saras’ plans for commercial production.
How is the rise of AI and high-performance computing changing the role of power delivery in system design?
As AI and high-performance computing systems become more power-dense, the power-delivery network is moving into the critical path of system design. It is no longer enough to optimize only the processor and advanced package. Designers must also minimize losses, maintain low PDN impedance, and deliver current quickly enough to support rapid workload transitions. That requires innovation across the components, materials, and architecture of the entire power-delivery path.
How is advanced packaging enabling a more efficient approach to power delivery?
Historically, power has travelled laterally across the board and package before reaching the processor. The industry is now moving toward more vertical approaches that bring voltage conversion, energy storage, and other power-delivery functions closer to the CPU, GPU, or memory. Embedding components within the PCB, package substrate, or chiplet environment can shorten the electrical path, reduce parasitic resistance and inductance, and use area more effectively.
How are customer priorities changing as more and more AI systems move toward commercialization?
Customer discussions are now becoming more practical. They are looking not only for higher component performance, but also for solutions that can be integrated predictably, customized for a particular architecture, tested before integration, and manufactured without introducing excessive cost or complexity. In other words, performance is essential, but manufacturability and scalability are becoming equally important.
An exploded layer-by-layer structure of Saras Micro Devices’ STILE technology, which embeds power-delivery passives directly into the semiconductor package substrate for AI accelerators.
STILE (Saras Tile) is an embedded integrated passive module for vertical power delivery – why develop this?
We see a growing need to integrate passive components at the PCB, package-substrate, and chiplet levels to meet the performance, power, area, and cost requirements of current and future AI and HPC systems. Saras developed this module to support that transition. It combines high-performance passive components with a configurable architecture and a repeatable integration approach, helping designers bring critical power-delivery functions closer to the processing elements without requiring a completely different manufacturing strategy for every design.
How does the module help to tackle the package-level power delivery challenge?
There are three parts to the challenge. First, passive components need to be positioned as close as practical to the processing elements to reduce the parasitic inductance associated with a longer delivery path. Second, the system needs sufficient local capacitance to respond to rapid changes in workload and current demand. Third, these capabilities must fit within a manufacturing approach that controls area, cost, and complexity. Our embedded integrated passive module is intended to address these requirements together rather than treating component performance and package integration as separate problems.
How can STILE improve the efficiency of AI and high-performance chips?
By design, the module is a configurable array of components for integration within a substrate core containing multiple embedded passive components. By placing high-density capacitance directly within the power-delivery structure, energy storage can be located much closer to the processor than with conventional approaches. Shortening that path can reduce parasitic losses and improve transient response. The array approach can also reduce the need to place and integrate many individual capacitor devices separately to meet total system requirements, while reducing the cost and complexity associated with manufacturing individual components at much lower density.
What are the key challenges involved in integrating capacitors and inductors directly into the chip package?
The challenge is not limited to the electrical performance of the individual components. Creating many separate cavities in a dense, expensive substrate can add manufacturing cost, yield risk, and routing complexity. We take a different approach by designing components to be embedded within commonly used core structures, either individually or as a pre-assembled and testable STILE array. The objective is to provide design flexibility while maintaining a more unified and repeatable method of integration at the substrate or PCB level.
How is Saras developing its technology roadmap to meet evolving power delivery network requirements?
Our roadmap begins with the passive components themselves. Saras determined that the available capacitor technologies did not meet our combination of density and integration requirements, so we developed a proprietary capacitor architecture. Today, the STILE concept is based on those capacitors, while inductive elements remain in development. Over time, we envision extending the platform to support a broader selection of qualified components, giving designers more flexibility to configure the passive array for their particular power-delivery architecture. All of this is built around a standardized integration method in a known-good array. We are aiming for customization without consequence, built around power delivery network requirements rather than a catalogue of standard components - all integrated into the core.
Do you have any examples of STILE in AI or high-performance computing applications?
Saras has built an interposer using our proprietary capacitors, demonstrating that the core integration concept is technically achievable. We are also engaged in product-level activity around potential capacitor and STILE applications.
With Saras’ pilot line in Chandler, Arizona, up and running how is the facility supporting the company’s path towards commercial production?
Our prototype and manufacturing line in Chandler, is operational and producing samples. The facility gives us the ability to customize individual components for form, fit, and function, as well as create STILE arrays that demonstrate the benefits of integrating a pretested group of passive components. The line also provides a foundation for incorporating inductive elements after that development is complete.
Shaun Bowers is senior vice president of product management at Saras Micro Devices. He previously spent 23 years at Amkor Technology, where he held senior leadership roles including vice president of power products and vice president of package development and technology integration.
